Investigation and minimization of inaccuracies in functional converters using structural modeling methods

Abstract

Relevance: the development of modern electronics, power conversion technology, and automatic control systems is inextricably linked to the need for fast and accurate processing of continuous signals. Despite comprehensive digitalization, analog functional converters remain indispensable in feedback loops, real-time systems, and complexes operating under severe electromagnetic interference and extreme temperatures, where the use of analog-to-digital/digital-to-analog converters and microprocessors is severely complicated. Pulse-width modulators possess enormous potential for building reliable computing nodes, such as multipliers and dividers. However, their application in modern circuit design is limited by the insufficient development of the general theory regarding instrumental error analysis. Traditional calculation methods fail to explicitly link the physical imperfections of components, such as hysteresis and residual voltages, to the final computational error. Therefore, developing structural modeling methods to identify and eliminate these errors is an urgent task; solving it will significantly increase the accuracy level of industrial electronics.

Aim: the purpose of this study is to develop a scientifically grounded methodology for the analysis and structural correction of errors in functional converters based on magnetic-transistor pulse-width modulators using causal-effect graph models.

Methods: the study employs a comprehensive analytical approach that includes electrical circuit theory, Boolean algebra, graph theory, and mathematical modeling methods for nonlinear dynamic systems. The primary analytical tool is the causal-effect model, constructed based on the directionality of energy conversion in each circuit section according to the cause-and-effect principle. Additionally, differential calculus methods are utilized to describe the electromagnetic processes of magnetization reversal in ferromagnetic cores exhibiting a rectangular hysteresis loop.

Results: a structural graph model of the dividing device was developed, enabling the classification of all error sources into four disjoint sets. It was mathematically proven that the dynamic magnetic field strength of the core induces a linearly increasing multiplicative error, whereas the transistor saturation voltage generates a constant additive error. Strict analytical conditions were established, and formulas for calculating the parameters of auxiliary circuits were derived to achieve complete hardware compensation of the identified errors. This approach was confirmed experimentally, demonstrating a reduction in the total circuit error to 0.2%.